|
|
|
|
|
|
|
|
|
|
| Day 1 | November 5 (Monday) | |||||||||||
| 08:30 - 18:00 |
Registration (Foyer, B2F) |
|||||||||||
| 09:00 - 10:30 |
Tutorial 1 When SAR Meets ΔΣ - A Tale of Two ADC Architectures - Nan Sun / University of Texas at Austin, USA (South+West+East Gate, B1F) |
|||||||||||
| 10:30 - 10:50 |
Break |
|||||||||||
| 10:50 - 12:20 |
Tutorial 2 Wireless ECG Acquisition and Cardiac Stimulation SOCs for Body Sensor Networks Shuenn-Yuh Lee / National Cheng Kung University, Taiwan (South+West+East Gate, B1F) |
|||||||||||
| 12:20 - 13:40 |
Lunch |
|||||||||||
| 13:40 - 15:10 |
Tutorial 3 Terahertz CMOS Technology for Beyond 5G Minoru Fujishima / Hiroshima University, Japan (South+West+East Gate, B1F) |
|||||||||||
| 15:10 - 15:30 |
Break |
|||||||||||
| 15:30 - 17:00 |
Tutorial 4 Memory System for Next Generation AI Kyomin Sohn / Samsung Electronics, Korea (South+West+East Gate, B1F) |
|||||||||||
| 17:00 - 19:00 |
SDC Exhibition (Foyer, B1F) |
FPGA Demo (Foyer, B1F) |
||||||||||
| 18:00 - 19:30 |
Welcome Reception (Far Eastern Grand Ballroom A+B, B2F) |
|||||||||||
| Day 2 | November 6 (Tuesday) | |||||||||||
| 07:45 - 18:00 |
Registration (Foyer, B2F) |
|||||||||||
| 08:30 - 08:50 |
Opening Ceremony (Far Eastern Grand Ballroom A+B, B2F) |
|||||||||||
| 08:50 - 09:35 |
Plenary Talk 1 Circuit Design in Nano-Scale CMOS Technologies Dr. Kevin Zhang / VP, Business Development, TSMC, Taiwan (Far Eastern Grand Ballroom A+B, B2F) |
|||||||||||
| 09:40 - 10:25 |
Plenary Talk 2 Open the New World of 5G Mr. Seizo ONOE / CTA, NTT DOCOMO & President, DOCOMO Tech., Japan (Far Eastern Grand Ballroom A+B, B2F) |
|||||||||||
| 10:25 - 10:50 |
Break |
|||||||||||
| 10:50 - 12:30 |
Industry 2 Advanced Techniques for Industrial Applications (Far Eastern Grand Ballroom A+B, B2F) |
ETA 3 Intelligent Sensor and Imager Systems (East Gate, B1F) |
SDC Exhibition (Foyer, B1F) |
FPGA Demo (Foyer, B1F) |
||||||||
| 12:30 - 13:30 |
Lunch |
|||||||||||
| 13:30 - 15:10 |
ACS 4 Power Converters and Sensors (North Gate, B1F) |
FPGA 5 FPGA-based AI Computing (South Gate, B1F) |
WLN 6 Optical Link and CDR (West Gate, B1F) |
RF 7 Millimeter-Wave Transceivers and Terahertz Sensors (East Gate, B1F) |
||||||||
| 15:10 - 15:30 | Break | |||||||||||
| 15:30 - 17:30 |
PD 8 : Panel Discussion (Far Eastern Grand Ballroom B, B2F) |
|||||||||||
| 17:30 - 19:00 |
Break |
|||||||||||
| 19:00 - 21:00 |
Banquet (Far Eastern Grand Ballroom A+B, B2F) |
|||||||||||
| Day 3 | November 7 (Wednesday) | |||||||||||
| 07:45 - 12:00 |
Registration (Foyer, B2F) |
|||||||||||
| 08:30 - 09:15 |
Plenary Talk 3 Practical Challenges in Supporting Functions in Memory Dr. Nam Sung Kim / SVP, Memory Division, Samsung, Korea (Far Eastern Grand Ballroom A+B, B2F) |
|||||||||||
| 09:20 - 10:05 |
Plenary Talk 4 AI Drive Domain Specific Processor Dr. Yi Kang / Chief Scientist & SVP, UNISOC, China (Tsinghua Unigroup) (Far Eastern Grand Ballroom A+B, B2F) |
|||||||||||
| 10:05 - 10:30 |
Break |
|||||||||||
| 10:30 - 12:35 |
ACS+DC 10 Analog and Data Converter Techniques (North Gate, B1F) |
ETA 11 Technology and Circuit Techniques for IoT (South Gate, B1F) |
MEM 12 Intelligent Memory System (West Gate, B1F) |
DCS 13 Circuit Technologies for Security Enhancement (East Gate, B1F) |
||||||||
| 12:35 - 13:40 |
Lunch |
|||||||||||
| 13:40 - 15:20 |
ACS 14 Inductive DC-DC Converters (North Gate, B1F) |
DCS 15 Energy-Efficient Circuits and Architectures (South Gate, B1F) |
WLN 16 Advanced Wireline Equalization (West Gate, B1F) |
RF 17 Oscillators and Synthesizers (East Gate, B1F) |
||||||||
| 15:20 - 15:50 |
Break |
|||||||||||
| 15:50 - 17:55 |
DC 18 (125) ADCs and Calibration Techniques (North Gate, B1F) |
DCS+FPGA 19 (100) Multimedia and Signal Processing Hardware (South Gate, B1F) |
SOC 20 (100) Intelligent Low-Power SoCs (West Gate, B1F) |
RF 21 (100) Low-Power RF Transmitters and Receivers (East Gate, B1F) |
||||||||
| 17:55 - 19:30 |
Farewell Social Hour (Foyer, B1F) |
|||||||||||